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Nonvolatile Memory 2-Kbit E2PROM with I2C Bus
SDA 2526-5
Preliminary Data
MOS IC
Features
q Word-organized programmable nonvolatile memory in q q q q q q q q q
n-channel floating-gate technology (E2PROM) 256 x 8-bit organization Supply voltage 5 V Serial 2-line bus for data input and output (I2C Bus) Reprogramming mode, 10 ms erase/write cycle Reprogramming by means of on-chip control (without external control) Check for end of programming process Data retention > 10 years More than 104 reprogramming cycles per address Compatible with SDA 2526. Exceptions: Conditions for total erase and current consumption ICC Ordering Code Q67100-H5095
P-DIP-8-1
Type SDA 2526-5
Package P-DIP-8-1
Circuit Description I2C Bus Interface The I2C Bus is a bidirectional 2-line bus for the transfer of data between various integrated circuits. It consists of a serial data line SDA and a serial clock line SCL. The data line requires an external pull-up resistor to VCC (open drain output stage). The possible operational states of the I2C Bus are shown in figure 1. In the quiescent state, both lines SDA and SCL are high, i.e. the output stage of the data line is disabled. As long a SCL remains "1", information changes on the data bus indicate the start or the end of data transfer between two components. The transition on SDA from "1" to "0" is a start condition, the transition from "0" to "1" is a stop condition. During a data transfer the information on the data bus will only change while the clock line SCL is "0". The information on SDA is valid as long as SCL is "1". In conjunction with an I2C Bus system, the memory component can operate as a receiver and as a transmitter (slave receiver or slave transmitter). Between a start and stop condition, information is always transmitted in byte-organized form. Between the falling edge of the eighth clock pulse and a ninth acknowledge clock pulse, the memory component sets the SDA-line to low as a confirmation of reception, if the chip select conditions have been met. During the output of data, the data output of the memory is high in impedance during the ninth clock pulse (acknowledge master). The signal timing required for the operation of the I2C Bus is summarized in figure 2.
Semiconductor Group
17
07.94
SDA 2526-5
Control Functions of the I2C Bus The memory component is controlled by the controller (master) via the I2C Bus in two operating modes: read-out cycle, and reprogramming cycle, including erase and write to a memory address. In both operating modes, the controller, as transmitter, has to provide 3 bytes and an additional acknowledge clock pulse to the bus after the start condition. During a memory read, at least nine additional clock pulses are required to accept the data from the memory and the acknowledge master, before the stop condition may follow. In the case of programming, the active programming process is only started by the stop condition after data input (see figure 3). The chip select word contains the 3 chip select bits CS0, CS1 and CS2, thus allowing 8 memory chips to be connected in parallel. Chip select is achieved when the three control bits logically correspond to the selected conditions at the select inputs. Check for End of Programming or Abortion of Programming Process If the chip is addressed during active reprogramming by entering CS/E, the programming process is terminated. If, however, it is addressed by entering CS/A, the entry will be ignored. Only after programming has been terminated will the chip respond to CS/A. This allows the user to check whether the end of the programming process has been reached (see figure 3). Memory Read After the input of the first two control words CS/E and WA, a resetting of the start condition and the input of the third control word CS/A, the memory is set ready to read. During acknowledge clock nine, the memory information is transferred in parallel mode to the shift register. Subsequent to the falling edge of the acknowledge clock, the data output is low impedance and the first data bit can be sampled (see figure 4). With every shift clock, an additional bit reaches the output. After reading a byte, the internal address counter is automatically incremented when the master receiver switches the data line to "low" during the ninth clock (acknowledge master). Any number of memory locations can thus be read one after the other. At address 256, an overflow to address 0 is initiated. With the stop condition, the data output returns to high-impedance mode. The internal sequence control of the memory component is reset from the read to the quiescent state with the stop condition.
Semiconductor Group
18
SDA 2526-5
Memory Reprogramming The reprogramming cycle of a memory word comprises an erase and a subsequent write process. During erase, all eight bits of the selected word are set into the "1" state. During write, "0" states are generated according to the information in the internal data register, i.e. according to the third input control word. After the 27th and last clock of the control word input, the active programming process is started by the stop condition. The active reprogramming process is executed under on-chip control. The time required for reprogramming depends on component deviation and data patterns. Therefore, with rated supply voltage, the erase/write process extends over max. 20 ms, or more typically, 10 ms. In the case of data word input without write request (write request is defined as data bit in data register set to "0"), the write process is suppressed and the programming time is shortened. During a subsequent programming of an already erased memory address, the erase process is suppressed again, so that the reprogramming time is also shortened. Important: Switch-On Mode and Chip Reset After the supply voltage VCC has been connected, the data output will be in high-impedance mode. As a rule, the first operating mode to be entered, should be the read process of a word address. As a result of the built-in "power-on reset" circuit, programming requests will not be accepted immediately after the supply voltage has been switched on. Total Erase Enter the control word CS/E, load the address register with address 0 and the data register with FF (hex) to erase the entire contents of the memory. Switch input CS2 to "open" immediately prior to generating the stop condition. The subsequent stop condition triggers a total erase. Upon termination of "total erase", CS2 must be reconnected to either 0 V or 4.5 V.
Semiconductor Group
19
SDA 2526-5
Pin Configuration (top view)
Pin Definitions and Functions Pin No. 1 2 3 4 5 6 7 8 Symbol Function Ground Chip select Chip select Chip select 0 VI 0.2 V; 4.5 VI VCC open, condition for delete of the complete memory Data line Clock line Test pin Supply voltage
VSS
CS0 CS1 CS2 SDA SCL TP
VCC
Semiconductor Group
20
SDA 2526-5
Block Diagram
Semiconductor Group
21
SDA 2526-5
Absolute Maximum Ratings TA = 25 C Parameter Supply voltage Input voltage Power dissipation Storage temperature Thermal resistance (system-air) Junction temperature Operating Range Supply voltage Ambient temperature Symbol min. Limit Values max. 6 6 130 - 40 125 100 85 V V mW C K/W C - 0.3 - 0.3 Unit
VCC VI PV Tstg Rth SA Tj
VCC TA
4.75 0
5.25 70
V C
Semiconductor Group
22
SDA 2526-5
Characteristics TA = 25 C Parameter Supply voltage Supply current Inputs Input voltages SDA/SCL Input voltages SDA/SCL Input currents Output Output current SDA Leakage current Inputs Input voltages CS0/CS1/CS2 Input voltages CS0/CS1/CS2 Input currents CS0/CS1/CS2 Clock frequency Reprogramming duration Input capacity Total erase Symbol min. Limit Values typ. 5.0 max. 5.25 20 V mA 4.75 Unit Test Condition
VCC IDD
VCC = 5.25 V
VIL VIH IIH
3.0
1.5
V V A
VCC
10
VIH = VCC
IQL IQH
3.0 10
mA A
VQL = 0.4 V VQH = VCC max
VIL VIH IIH fSCL tprog CI tGL
10 4.5
0.2
V V A kHz ms pF ms CS2 = open erase and write
VCC
100 100 20 10 20
VCC = 5.25 V
Semiconductor Group
23
SDA 2526-5
Test Circuit
Application Circuit Semiconductor Group 24
SDA 2526-5
Diagrams
Figure 1 Operation States of the I2C Bus
Semiconductor Group
25
SDA 2526-5
Figure 2 Timing Conditions for the I2C Bus (high-speed mode)
Parameter Minimum time the bus must be free before a new transmission can start Start condition hold time Clock low period Clock high period Start condition set-up time, only valid for repeated start code Data set-up time Rise time of both the SDA- and SCL-line Fall time of both the SDA- and SCL-line Stop condition set-up time Hold time data
of the falling edge of SCL.
Symbol min.
Limit Values max.
Unit
tBUF tHD;STA tLOW tHIGH tSU;STA tSU;DAT tR tF tSU;STO tHD;DAT
4.7 4.0 4.7 4.0 4.7 250 1 300 4.7 0*)
s s s s s ns s ns s
* Note that a transmitter must internally provide at least a hold time to bridge the undefined region (max. 300 ns)
Semiconductor Group
26
SDA 2526-5
Figure 3 Programming Control word input ST CS/E As WA As DE As SP (the reprogramming starts after this stop condition)
Check for program end
ST
CS/A
As
1. when As = 1 programming is not finished 2. when As = 0 programming is finished
Program interruption by
ST
CS/E
As
Figure 4 Read Control word input read a) complete (with word address input) ST CS/E As WA As ST CS/A As DA n bytes Am DA Last byte Am SP
Automatic incrementation of the word address b) shortened: Bit 0 ... 7 the last adapted word address keep unchanged
ST
CS/A
As
DA n bytes
Am
DA Last byte
Am
SP
Autoincrement before stop condition
Am = 0 Am = 1
Semiconductor Group
27
SDA 2526-5
Control Word Table Clock No. CS/E CS/A WA DE DA 1 1 1 A7 D7 D7 2 0 0 A6 D6 D6 3 1 1 A5 D5 D5 4 0 0 A4 D4 D4 5 CS2 CS2 A3 D3 D3 6 CS1 CS1 A2 D2 D2 7 CS0 CS0 A1 D1 D1 8 0 1 A0 D0 D0 9 0 0 0 0 0/1 (Acknowledge) through memory through memory through memory through memory through master
Control Word Input Key CS/E CS/A WA DE DA D0 to D7 ST SP As Am CS0, CS1, CS2 A0 to A7 Chip select for data input into memory Chip select for data output out of memory Memory word address Data word for memory Data word read out of memory Data bits Start condition Stop condition Acknowledge bit from memory Acknowledge bit from master Chip select bits Memory word address bits
Semiconductor Group
28

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